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The copyright of a submitted article is only transferred to the publishers if and when the article is accepted for publication. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, electrostatic, mechanical, photocopying, recording or otherwise without the prior written permission of the publishers.
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Automatic test pattern generation for iterative logic arrays
Abstract
In this work, measures to evaluate fault-effect propagation of test patterns of a C-test are first formulated. Next, the repetition property of the test patterns is exploited to develop a method for generating C-tests for ILAs under the cell fault model. Based on the results of test generation, the method identifies points of insertion of extra hardware in order to achieve C-testability for the target array. Finally, results obtained by applying the proposed method to generate minimum C-tests for a few well-known arithmetic arrays are shown.
Journal of Science and Technology Vol.24(2) 2004: 1-7
Journal of Science and Technology Vol.24(2) 2004: 1-7
