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Published:
May 22, 2018Keywords:
Advanced Encryption Standard (AES) Field Programmable Gate Array (FPGA) High Level Language (HLL) Integrated Synthesis Environment (ISE).
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Retracted: Loop unrolling implementation of an AES Algorithm using Xilinx System Generator
Abstract
This article was withdrawn and retracted by the Journal of Fundamental and Applied Sciences and has been removed from AJOL at the request of the journal Editor in Chief and the organisers of the conference at which the articles were presented (www.iccmit.net). Please address any queries to editor@jfas.info.
