Temperature activated tunnelling processes in aSe/pSi heterojunction

Abstract

Heterojunction is fabricated by depositing amorphous selenium (aSe) on p-type crystalline silicon (pSi) subtract of 3-7Ω cm resistivity by vacuum evaporation method. DC electrical conduction record from 82k up to room temperature (RT). Results of current – voltage (I-V)
and capacitance – voltage (C-V) measurements are compared with the two tunneling processes purposed by Riben – Feucht and Matsuura et al. At high temperature (>140k), the forward bias is T dependent, while the reverse bias gives an exponential (-¹/_T) dependence.
However at low temperatures (<140k), the conductivity is constant. It is deducted that tunnel hopping of electrons is prevalent in the aSe side while barrier tunneling of holes occur in the pSi of the interface. Recombination of electron and hole becomes predominant at high
negative bias due to whole injection into the interface coming from the pSi.

Keywords: Temperature, Tunneling, Resistivity, Vacuum, Evaporation.